发明申请
US20090128216A1 SYSTEM AND METHOD FOR TIME-TO-VOLTAGE CONVERSION WITH LOCK-OUT LOGIC
有权
具有锁定逻辑的时间到电压转换的系统和方法
- 专利标题: SYSTEM AND METHOD FOR TIME-TO-VOLTAGE CONVERSION WITH LOCK-OUT LOGIC
- 专利标题(中): 具有锁定逻辑的时间到电压转换的系统和方法
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申请号: US12199020申请日: 2008-08-27
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公开(公告)号: US20090128216A1公开(公告)日: 2009-05-21
- 发明人: Naresh Kesavan Rao , Brian David Yanoff , Yanfeng Du , Jianjun Guo
- 申请人: Naresh Kesavan Rao , Brian David Yanoff , Yanfeng Du , Jianjun Guo
- 主分类号: G06G7/18
- IPC分类号: G06G7/18
摘要:
An event time stamping system comprising a current source, an integrator comprising an input and an output, and configured to output a voltage proportional to the length of time the current source is coupled to the input, and one or more switches configured to couple the current source to the input of the integrator upon receipt of an event signal and configured to de-couple the current source from the input of the integrator upon receipt of a control trigger. The system further comprises a lock-out signal generator configured to generate a lock-out signal, and a controller coupled to the one or more switches, wherein the controller is configured to generate the control trigger based on the lock-out signal to ensure a minimum integration time.