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发明申请
US20090137069A1 Chip packaging process including simpification and mergence of burn-in test and high temperature test 审中-公开
芯片封装工艺包括烧录测试和高温测试的简化和合并

Chip packaging process including simpification and mergence of burn-in test and high temperature test
摘要：
A chip packaging process integrates a burn-in test or a high temperature test to simplify overall packaging and testing process flow. One or more chips are disposed on one or more units of a substrate strip where the substrate strip has a plurality of electrical open sections at the plating lines to electrically isolate the external pads between different units. After electrical connection and encapsulation, a burn-in test is executed at the same time of a post mold curing step, with a high-temperature testing if necessary. Therefore, the chips on the substrate strip has been gone through the burn-in test during the encapsulant is completely cured at the post mold curing step and the burn-in test is finished before the singulation step to reduce the overall testing time.
摘要（中）：

芯片封装过程集成了老化测试或高温测试，以简化整个封装和测试流程。 一个或多个芯片设置在衬底条的一个或多个单元上，其中衬底带在电镀线处具有多个电开路部分，以在不同单元之间电隔离外部焊盘。 在电连接和封装之后，在后模具固化步骤的同时进行老化测试，如果需要进行高温测试。 因此，在模塑固化步骤期间封装剂完全固化之前，衬底条上的芯片已经经过老化测试，并且在分离步骤之前完成老化测试以减少整体测试时间。

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