发明申请
- 专利标题： REDUCING GATE CD BIAS IN CMOS PROCESSING
- 专利标题（中）： 降低CMOS加工中的门偏移
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申请号： US12241798申请日： 2008-09-30
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公开(公告)号： US20090166629A1公开(公告)日： 2009-07-02
- 发明人: Freidoon Mehrad , Jinhan Choi , Frank Scott Johnson
- 申请人： Freidoon Mehrad , Jinhan Choi , Frank Scott Johnson
- 申请人地址： US TX Dallas
- 专利权人： Texas Instruments Incorporated
- 当前专利权人： Texas Instruments Incorporated
- 当前专利权人地址： US TX Dallas
- 主分类号： H01L21/8238
- IPC分类号： H01L21/8238 ; H01L27/092
摘要：
A method of forming an integrated circuit having an NMOS transistor and a PMOS transistor is disclosed. The method includes performing pre-gate processing in a NMOS region and a PMOS region over and/or in a semiconductor body, and depositing a polysilicon layer over the semiconductor body in both the NMOS and PMOS regions. The method further includes performing a first type implant into the polysilicon layer in one of the NMOS region and PMOS region, and performing an amorphizing implant into the polysilicon layer in both the NMOS and PMOS regions, thereby converting the polysilicon layer into an amorphous silicon layer. The method further includes patterning the amorphous silicon layer to form gate electrodes, wherein a gate electrode resides in both the NMOS and PMOS regions.
公开/授权文献
- US07910422B2 Reducing gate CD bias in CMOS processing 公开/授权日：2011-03-22
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