发明申请
- 专利标题: CAPACITIVE LOAD DRIVING CIRCUIT
- 专利标题(中): 电容负载驱动电路
-
申请号: US11720507申请日: 2006-01-11
-
公开(公告)号: US20090167371A1公开(公告)日: 2009-07-02
- 发明人: Hiroshi Ando , Akihiro Maejima , Hiroki Matsunaga , Jinsaku Kaneda , Eisaku Maeda
- 申请人: Hiroshi Ando , Akihiro Maejima , Hiroki Matsunaga , Jinsaku Kaneda , Eisaku Maeda
- 申请人地址: JP OSAKA
- 专利权人: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
- 当前专利权人: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
- 当前专利权人地址: JP OSAKA
- 优先权: JP2005-003665 20050111
- 国际申请: PCT/JP2006/300188 WO 20060111
- 主分类号: H03K3/00
- IPC分类号: H03K3/00
摘要:
It is aimed to reduce the area of an output circuit in a capacitive load driving circuit capable of high voltage output, such as a PDP scan driver for driving a plasma display panel. To achieve this, there are provided an arbitrary number of N-type MOS transistors 001, 002, . . . , and 003 including grounded sources and gates receiving a control signal, diodes 004, 005, . . . , and 006 paired with the N-type MOS transistors 001, 002, . . . , and 003, respectively, and including cathodes connected to drains of the N-type MOS transistors 001, 002, . . . , and 003 and anode, all connected to a first node 044, the number of diodes being the same as the number of N-type MOS transistors, and a first P-type MOS transistor 015 having a drain connected to the first node 044, a gate receiving a control signal and a source connected to a high voltage source.
信息查询