An n-type embedded layer is formed in an N-LV region of a SRAM cell region after an element isolation insulating film is formed on a p-type Si substrate. Thereafter, a p-well and an n-well are formed. In formation of a channel-doped layer, ion implantation is also performed into the N-LV region of the SRAM cell region in parallel with ion implantation into an N-LV of a logic circuit region. Ion-implantation is further performed into the N-LV region of the SRAM cell region in parallel with ion implantation into an N-MV of an I/O region.