发明申请
- 专利标题： Dual Function Adder for Computing a Hardware Prefetch Address and an Arithmetic Operation Value
- 专利标题（中）： 用于计算硬件预取地址和算术运算值的双功能加法器
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申请号： US12041694申请日： 2008-03-04
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公开(公告)号： US20090228688A1公开(公告)日： 2009-09-10
- 发明人: Ajay Anant Ingle , Erich James Plondke , Lucian Codrescu
- 申请人： Ajay Anant Ingle , Erich James Plondke , Lucian Codrescu
- 申请人地址： US CA San Diego
- 专利权人： QUALCOMM INCORPORATED
- 当前专利权人： QUALCOMM INCORPORATED
- 当前专利权人地址： US CA San Diego
- 主分类号： G06F9/30
- IPC分类号： G06F9/30
摘要：
A system including a dual function adder is described. In one embodiment, the system includes an adder. The adder is configured for a first instruction to determine an address for a hardware prefetch if the first instruction is a hardware prefetch instruction. The adder is further configures for the first instruction to determine a value from an arithmetic operation if the first instruction is an arithmetic operation instruction.