发明申请
- 专利标题: Circuit and Method for a Vdd Level Memory Sense Amplifier
- 专利标题(中): 用于Vdd级存储器检测放大器的电路和方法
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申请号: US12046276申请日: 2008-03-11
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公开(公告)号: US20090231939A1公开(公告)日: 2009-09-17
- 发明人: Kuoyuan Peter Hsu , Young Suk Kim , Bing Wang , Ming Chieh Huang
- 申请人: Kuoyuan Peter Hsu , Young Suk Kim , Bing Wang , Ming Chieh Huang
- 主分类号: G11C7/08
- IPC分类号: G11C7/08 ; G11C7/12
摘要:
A circuit and method for a sense amplifier for sensing the charge stored by a memory cell is disclosed. The memory cell is coupled to a bit line, a complementary bit line and a differential sense amplifier is coupled to the bit line and the complementary bit line. A control signal couples a reference voltage to the complementary bit line. A positive precharge voltage is applied to the bit line and complementary bit line prior to the sense amplifier being enabled. The memory cell outputs a voltage to the bit line responsive to a word line, and the sense amplifier senses the differential voltage between the bit line and the complementary bit line responsive to a sense enable signal. A voltage regulator for generating the reference voltage, preferably about 80% of a positive supply voltage, is disclosed. A method of sensing data stored by a memory cell is disclosed.
公开/授权文献
- US07848166B2 Circuit and method for a Vdd level memory sense amplifier 公开/授权日:2010-12-07
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