发明申请
US20090246927A1 INCREASING STRESS TRANSFER EFFICIENCY IN A TRANSISTOR BY REDUCING SPACER WIDTH DURING THE DRAIN/SOURCE IMPLANTATION SEQUENCE
有权
通过在排水/源植入序列期间减少间隔宽度在晶体管中增加应力传递效率
- 专利标题： INCREASING STRESS TRANSFER EFFICIENCY IN A TRANSISTOR BY REDUCING SPACER WIDTH DURING THE DRAIN/SOURCE IMPLANTATION SEQUENCE
- 专利标题（中）： 通过在排水/源植入序列期间减少间隔宽度在晶体管中增加应力传递效率
-
申请号： US12271162申请日： 2008-11-14
-
公开(公告)号： US20090246927A1公开(公告)日： 2009-10-01
- 发明人: Maciej Wiatr , Roman Boschke , Anthony Mowry
- 申请人： Maciej Wiatr , Roman Boschke , Anthony Mowry
- 优先权： DE102008016512.3 20080331
- 主分类号： H01L21/336
- IPC分类号： H01L21/336
摘要：
By forming a single spacer element and reducing the size thereof by a well-controllable etch process, a complex lateral dopant profile may be obtained at reduced process complexity compared to conventional triple spacer approaches in forming drain and source regions of advanced MOS transistors.
公开/授权文献
信息查询
IPC分类:
