A thin film transistor array panel includes a substrate, a gate line disposed on the substrate and having a gate electrode, a gate insulating layer disposed on the gate line, a data line disposed on the gate insulating layer and crossing the gate line, a source electrode connected to the data line, a drain electrode spaced apart from the source electrode, a semiconductor layer connected to the source and drain electrodes to form a channel, a light blocking layer disposed on the semiconductor layer to block light incident to the semiconductor layer, and a pixel electrode contacting the drain electrode.