发明申请
US20090269926A1 POLYGRAIN ENGINEERING BY ADDING IMPURITIES IN THE GAS PHASE DURING CHEMICAL VAPOR DEPOSITION OF POLYSILICON
审中-公开
通过在多晶硅化学气相沉积期间在气相中添加污染物进行聚合工程
- 专利标题: POLYGRAIN ENGINEERING BY ADDING IMPURITIES IN THE GAS PHASE DURING CHEMICAL VAPOR DEPOSITION OF POLYSILICON
- 专利标题(中): 通过在多晶硅化学气相沉积期间在气相中添加污染物进行聚合工程
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申请号: US12110594申请日: 2008-04-28
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公开(公告)号: US20090269926A1公开(公告)日: 2009-10-29
- 发明人: Abhishek Dube , Ashima B. Chakravarti , Anthony I. Chou , Wei He , Dominic J. Schepis
- 申请人: Abhishek Dube , Ashima B. Chakravarti , Anthony I. Chou , Wei He , Dominic J. Schepis
- 申请人地址: US NY Armonk
- 专利权人: INTERNATIONAL BUSINESS MACHINES CORPORATION
- 当前专利权人: INTERNATIONAL BUSINESS MACHINES CORPORATION
- 当前专利权人地址: US NY Armonk
- 主分类号: H01L21/44
- IPC分类号: H01L21/44
摘要:
A method of forming at least one gate conductor of a complementary metal oxide semiconductor performs a chemical vapor deposition process of polysilicon over a surface where a polysilicon gate is to be located. This deposition can be performed through a mask to form gate structures directly, or a later patterning process can pattern the polysilicon into gate structures. During the chemical vapor deposition process, the method adds impurities in the chemical vapor deposition process to optimize the grain size of the polysilicon according to a number of different methods.
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