Cost of testing is reduced. An SiP (1) comprises an AD chip (2) and a logic chip (3) that perform transmission and reception of data. The AD chip (2) comprises AD conversion circuits (12a and 12b) that generate parallel data, parallel-serial conversion circuits (13a and 13b) that divide parallel data generated by the AD conversion circuits (12a and 12b) and perform time-based sorting, and selection circuits (14a and 14b) that select any of: output data of the parallel-serial conversion circuits (13a and 13b), or divided data obtained by dividing the parallel data so as to enable transmission of each thereof by said plural paths, and output to the logic chip (3). The logic chip (3) comprises serial-parallel conversion circuits (15a and 15b) that recover original parallel data from data sorted in a time-based manner, and a selection circuit (16) that selects: original parallel data obtained by combining the divided data, or original parallel data recovered by the serial-parallel conversion circuits (15a and 15b), and outputs to a terminal (18).