Invention Application
- Patent Title: Three-Dimensional Integrated Circuits and Techniques for Fabrication Thereof
- Patent Title (中): 三维集成电路及其制造技术
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Application No.: US12131988Application Date: 2008-06-03
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Publication No.: US20090294814A1Publication Date: 2009-12-03
- Inventor: Solomon Assefa , Kuan-Neng Chen , Steven J. Koester , Yurii A. Vlasov
- Applicant: Solomon Assefa , Kuan-Neng Chen , Steven J. Koester , Yurii A. Vlasov
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Main IPC: H01L31/00
- IPC: H01L31/00 ; H01L21/00

Abstract:
Integrated circuits having complementary metal-oxide semiconductor (CMOS) and photonics circuitry and techniques for three-dimensional integration thereof are provided. In one aspect, a three-dimensional integrated circuit comprises a bottom device layer and a top device layer. The bottom device layer comprises a substrate; a digital CMOS circuitry layer adjacent to the substrate; and a first bonding oxide layer adjacent to a side of the digital CMOS circuitry layer opposite the substrate. The top device layer comprises an analog CMOS and photonics circuitry layer formed in a silicon-on-insulator (SOI) layer having a buried oxide (BOX) with a thickness of greater than or equal to about 0.5 micrometers; and a second bonding oxide layer adjacent to the analog CMOS and photonics circuitry layer. The bottom device layer is bonded to the top device layer by an oxide-to-oxide bond between the first bonding oxide layer and the second bonding oxide layer.
Public/Granted literature
- US07897428B2 Three-dimensional integrated circuits and techniques for fabrication thereof Public/Granted day:2011-03-01
Information query
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