发明申请
- 专利标题: Methodology and Apparatus for Reduction of Soft Errors in Logic Circuits
- 专利标题(中): 减少逻辑电路中软错误的方法和设备
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申请号: US12484708申请日: 2009-06-15
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公开(公告)号: US20090309627A1公开(公告)日: 2009-12-17
- 发明人: Nagarajan Ranganathan , Koustav Bhattacharya
- 申请人: Nagarajan Ranganathan , Koustav Bhattacharya
- 主分类号: H03K19/003
- IPC分类号: H03K19/003 ; H03K19/20 ; H03K19/007
摘要:
The present invention includes a circuit-level system and method for preventing the propagation of soft errors in logic cells. A radiation jammer circuit in accordance with the present invention, including an RC differentiator and a depletion mode MOS circuit, when inserted at the output of a logic cell, significantly reduces the propagation of transient glitches. The radiation jammer circuit is a novel transistor-level optimization technique, which has been used to reduce soft errors in a logic circuit. A method to insert radiation jammer cells on selective nodes in a logic circuit for low overheads in terms of delay, power, and area is also introduced.
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