发明申请
US20090327981A1 Semiconductor device or printed wiring board design method and design support system that implements settings by using a semiconductor device model that expresses parasitic elements that occur when packaged
审中-公开
半导体器件或印刷线路板设计方法和设计支持系统,通过使用表示在封装时发生的寄生元件的半导体器件模型来实现设置
- 专利标题: Semiconductor device or printed wiring board design method and design support system that implements settings by using a semiconductor device model that expresses parasitic elements that occur when packaged
- 专利标题(中): 半导体器件或印刷线路板设计方法和设计支持系统,通过使用表示在封装时发生的寄生元件的半导体器件模型来实现设置
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申请号: US12457930申请日: 2009-06-25
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公开(公告)号: US20090327981A1公开(公告)日: 2009-12-31
- 发明人: Satoshi Nakamura , Tsutomu Hara , Mitsuaki Katagiri , Yukitoshi Hirose , Satoshi Itaya , Ken Iwakura
- 申请人: Satoshi Nakamura , Tsutomu Hara , Mitsuaki Katagiri , Yukitoshi Hirose , Satoshi Itaya , Ken Iwakura
- 申请人地址: JP Tokyo
- 专利权人: Elpida Memory, Inc.
- 当前专利权人: Elpida Memory, Inc.
- 当前专利权人地址: JP Tokyo
- 优先权: JP2008-165628 20080625
- 主分类号: G06F17/50
- IPC分类号: G06F17/50
摘要:
Correction circuit models are acquired for correcting electrical characteristic parameters that change upon mounting on a board. The correction circuit models are added to a separate model that represents a separate semiconductor device in isolation to create a semiconductor device model that represents the semiconductor device in a board-mounted state. An equivalent circuit model that represents an adjustment-object system is connected to the semiconductor device model that was created, and based on the semiconductor device model to which the equivalent circuit model is connected, adjustment-object values relating to the adjustment-object system are calculated. These adjustment-object values are compared with limit values that were determined in advance, and based on the results of comparison, a design guide is determined for adjusting the adjustment-object system.
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