发明申请
- 专利标题: Integrated Semiconductor Outline Package
- 专利标题(中): 集成半导体外形封装
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申请号: US12513906申请日: 2006-12-05
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公开(公告)号: US20100007006A1公开(公告)日: 2010-01-14
- 发明人: Stanley Job Doraisamy , Wae Chet Young
- 申请人: Stanley Job Doraisamy , Wae Chet Young
- 国际申请: PCT/SG06/00379 WO 20061205
- 主分类号: H01L23/50
- IPC分类号: H01L23/50
摘要:
A transistor outline package is provided for a semiconductor integrated device suitable for use in a control module of an automobile for connection between a printed circuit board and a bus bar of such a module. The package includes a package housing, having a first end suitable for mounting to a PCB and which has a width. The package is also formed with a leadframe which includes a heat sink and ground plane blade suitable for connection to a bus bar, a plurality of connector leads suitable for connection to a PCB and at least one source tab lead suitable for connection to a module connector of such a control module. The plurality of connection leads and the source tab lead extend from the first end of the package housing side by side in the direction along and within the width of the first end of the package housing.
公开/授权文献
- US08169069B2 Integrated semiconductor outline package 公开/授权日:2012-05-01
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