发明申请
US20100017690A1 METHOD AND APPARATUS FOR LOW LATENCY PROPORTIONAL PATH IN A DIGITALLY CONTROLLED SYSTEM
有权
用于数字控制系统中低延迟比例路径的方法和装置
- 专利标题： METHOD AND APPARATUS FOR LOW LATENCY PROPORTIONAL PATH IN A DIGITALLY CONTROLLED SYSTEM
- 专利标题（中）： 用于数字控制系统中低延迟比例路径的方法和装置
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申请号： US12175012申请日： 2008-07-17
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公开(公告)号： US20100017690A1公开(公告)日： 2010-01-21
- 发明人: Alexander V. Rylyakov , Jose A. Tierno
- 申请人： Alexander V. Rylyakov , Jose A. Tierno
- 主分类号： H04L1/00
- IPC分类号： H04L1/00 ; G06F11/00
摘要：
A digitally controlled circuit and method includes an error input coupled to a proportional path. The proportional path includes a selector which directly receives the error input as a select signal. The selector receives a proportional control weight from a location other than the proportional path wherein the proportional control weight is input to a digitally controlled oscillator (DCO).
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