- 专利标题: Method for manufacturing package on package with cavity
- 专利标题(中): 封装封装封装方法
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申请号: US12585235申请日: 2009-09-09
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公开(公告)号: US20100022052A1公开(公告)日: 2010-01-28
- 发明人: Jee-Soo Mok , Chang-Sup Ryu , Dong-Jin Park
- 申请人: Jee-Soo Mok , Chang-Sup Ryu , Dong-Jin Park
- 申请人地址: KR Suwon
- 专利权人: SAMSUNG ELECTRO-MECHANICS CO., LTD.
- 当前专利权人: SAMSUNG ELECTRO-MECHANICS CO., LTD.
- 当前专利权人地址: KR Suwon
- 优先权: KR10-2006-0014917 20060216
- 主分类号: H01L21/60
- IPC分类号: H01L21/60
摘要:
A manufacturing method of a package on package with a cavity. The method can include forming a first upper substrate cavity in one side of an upper substrate; mounting an upper semiconductor chip on the other side of the upper substrate; forming a lower substrate cavity in one side of a lower substrate; mounting a lower semiconductor chip in the lower substrate cavity formed in the lower substrate; and stacking the upper substrate above the lower substrate such that the first upper substrate cavity accommodates a part of the lower semiconductor chip. The package on package and a manufacturing method thereof can reduce the overall thickness of the package by forming cavities in both upper and lower substrates to accommodate a semiconductor chip mounted in the lower substrate.
公开/授权文献
- US07901985B2 Method for manufacturing package on package with cavity 公开/授权日:2011-03-08
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