发明申请
US20100046601A1 HIGH SPEED RECEIVE EQUALIZER ARCHITECTURE 有权
高速接收均衡器结构

HIGH SPEED RECEIVE EQUALIZER ARCHITECTURE
摘要:
Various example embodiments are disclosed. According to an example embodiment, an apparatus may include a continuous time filter, a decision feedback equalizer, a clock and data recovery circuit, and an adaptation circuit. The adaptation circuit may be configured to adapt equalization according to at least one dithering algorithm by adjusting a delay adjust signal based on a mean square error of equalized data signals.
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