An architecture for protecting circuitry used for signal communications between a frequency translation module (20) and a decoder (60) from transient voltage surges. According to an exemplary embodiment, the apparatus comprises a first signal path between a transmission line and a first reference potential, comprising a high impedance negative surge path; and a second signal path between the transmission line and the first reference potential, comprising a high impedance positive surge path, a low inductance surge path and a DC blocker circuit, wherein said high impedance positive surge path is configured in series with said low inductance surge path and said DC blocker circuit, wherein each of said low inductance surge path and said DC blocker circuit are coupled between said high impedance positive surge path and said source of reference potential.