发明申请
- 专利标题: Clock control of state storage circuitry
- 专利标题(中): 状态存储电路的时钟控制
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申请号: US12232187申请日: 2008-09-11
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公开(公告)号: US20100060321A1公开(公告)日: 2010-03-11
- 发明人: Stephen Andrew Kvinta , Marlin Wayne Frederick , Chih-Wei Huang
- 申请人: Stephen Andrew Kvinta , Marlin Wayne Frederick , Chih-Wei Huang
- 申请人地址: GB Cambridge
- 专利权人: ARM Limited
- 当前专利权人: ARM Limited
- 当前专利权人地址: GB Cambridge
- 主分类号: H03K19/096
- IPC分类号: H03K19/096 ; H03K3/289 ; H03K3/037
摘要:
State storage circuitry is described comprising a master-slave latch having tristate inverter circuitry 2 at its functional input and tristate scan signal insertion circuitry 12 for inserting scan data. The tristate scan signal insertion circuitry 12 is controlled by a first clock signal nclk and a second clock signal bclk. The tristate inverter circuitry 2 is controlled by a third clock signal nfclk and a fourth clock signal flck. The clock generating circuitry holds the third and fourth clock signals at fixed values which tristate the tristate inverter circuitry 2 when in scan mode. This moves scan control logic out of the function path comprising the tristate inverter circuitry into the clock control circuitry.
公开/授权文献
- US07893722B2 Clock control of state storage circuitry 公开/授权日:2011-02-22