A microcomputer in accordance with an exemplary embodiment of the preset invention include an instruction decoder 14 that decodes a branch multiple instruction including a conditional branch instruction to be executed at a first execution stage and a first operation instruction to be executed at a second execution stage, and a sequential operation instruction including a second operation instruction to be executed at the second execution stage, operation information storage circuits 15 and 16 that store first operation information corresponding to the first operation instruction, a branch condition decision circuit 18 that determines the satisfaction/non-satisfaction of a branch condition based on the conditional branch instruction and outputs a decision result signal J1, a selector 17 that outputs the first operation information stored in the operation information storage circuits 15 and 16 if the decision result signal J1 indicates one of the satisfaction and non-satisfaction states of the branch condition, and a computing unit 21 that carries out an operation based on operation information output by the selector 17.