发明申请
US20100095090A1 BARRIER SYNCHRONIZATION METHOD, DEVICE, AND MULTI-CORE PROCESSOR
有权
BARRIER同步方法，设备和多核处理器
- 专利标题： BARRIER SYNCHRONIZATION METHOD, DEVICE, AND MULTI-CORE PROCESSOR
- 专利标题（中）： BARRIER同步方法，设备和多核处理器
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申请号： US12638746申请日： 2009-12-15
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公开(公告)号： US20100095090A1公开(公告)日： 2010-04-15
- 发明人: Hideyuki UNNO , Masaki Ukai , Matthew Depetro
- 申请人： Hideyuki UNNO , Masaki Ukai , Matthew Depetro
- 申请人地址： JP Kanagawa
- 专利权人： FUJITSU LIMITED
- 当前专利权人： FUJITSU LIMITED
- 当前专利权人地址： JP Kanagawa
- 主分类号： G06F15/76
- IPC分类号： G06F15/76 ; G06F9/02 ; G06F12/08
摘要：
A barrier synchronization device for realizing barrier synchronization of at least 2 processor cores belonging to a same synchronization group among a plurality of processor cores is included in a multi-core processor having a plurality of processor cores, and when two or more processor cores in that multi-core processor belong to the same synchronization group, the included barrier synchronization device is used for realizing barrier synchronization.
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