发明申请
US20100115522A1 MECHANISM TO CONTROL HARDWARE MULTI-THREADED PRIORITY BY SYSTEM CALL
有权
通过系统呼叫控制硬件多线程优先级的机制
- 专利标题: MECHANISM TO CONTROL HARDWARE MULTI-THREADED PRIORITY BY SYSTEM CALL
- 专利标题(中): 通过系统呼叫控制硬件多线程优先级的机制
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申请号: US12261275申请日: 2008-10-30
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公开(公告)号: US20100115522A1公开(公告)日: 2010-05-06
- 发明人: Vaijayanthimala K. Anand , Joerg Droste , Bruce Mealey , Bret R. Olszewski
- 申请人: Vaijayanthimala K. Anand , Joerg Droste , Bruce Mealey , Bret R. Olszewski
- 申请人地址: US NY Armonk
- 专利权人: International Business Machines Corporation
- 当前专利权人: International Business Machines Corporation
- 当前专利权人地址: US NY Armonk
- 主分类号: G06F9/46
- IPC分类号: G06F9/46 ; G06F15/00
摘要:
A method, a system and a computer program product for controlling the hardware priority of hardware threads in a data processing system. A Thread Priority Control (TPC) utility assigns a primary level and one or more secondary levels of hardware priority to a hardware thread. When a hardware thread initiates execution in the absence of a system call, the TPC utility enables execution based on the primary level. When the hardware thread initiates execution within a system call, the TPC utility dynamically adjusts execution from the primary level to the secondary level associated with the system call. The TPC utility adjusts hardware priority levels in order to: (a) raise the hardware priority of one hardware thread relative to another; (b) reduce energy consumed by the hardware thread; and (c) fulfill requirements of time critical hardware sections.
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