发明申请
US20100115765A1 Layout verification apparatus, layout apparatus, layout verification method, layout verification program, and wiring forming method
审中-公开
布局验证装置,布局装置,布局验证方法,布局验证程序和布线形成方法
- 专利标题: Layout verification apparatus, layout apparatus, layout verification method, layout verification program, and wiring forming method
- 专利标题(中): 布局验证装置,布局装置,布局验证方法,布局验证程序和布线形成方法
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申请号: US12585441申请日: 2009-09-15
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公开(公告)号: US20100115765A1公开(公告)日: 2010-05-13
- 发明人: Takeshi Hamamoto
- 申请人: Takeshi Hamamoto
- 申请人地址: JP Kawasaki
- 专利权人: NEC ELECTRONICS CORPORATION
- 当前专利权人: NEC ELECTRONICS CORPORATION
- 当前专利权人地址: JP Kawasaki
- 优先权: JP290083/2008 20081112
- 主分类号: H01R43/00
- IPC分类号: H01R43/00 ; G06F17/50
摘要:
The layout verification apparatus includes: a verification unit for obtaining mask data indicating a mask pattern to be drawn on a mask based on layout and wiring data indicating positions of a group of primitive cells and positions of connection wires connected to the group of primitive cells, and for verifying a position of the mask pattern based on the mask data, so as to detect an error part; and a correction hint creating unit for creating correction hint information based on the error part, and for sending the correction hint information to a layout and wiring unit for correcting the layout and wiring data. The correction hint creating unit obtains terminal information indicating positions of a group of terminals included in the group of primitive cells and creates the correction hint information based on the terminal information so that the positions of the group of terminals are not changed by the layout and wiring unit.
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