发明申请
- 专利标题: LEVERAGING LOW-LATENCY MEMORY ACCESS
- 专利标题(中): 引导低延迟存储器访问
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申请号: US12269877申请日: 2008-11-12
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公开(公告)号: US20100121865A1公开(公告)日: 2010-05-13
- 发明人: Kushagra V. Vaid , Gaurav Sareen
- 申请人: Kushagra V. Vaid , Gaurav Sareen
- 申请人地址: US WA Redmond
- 专利权人: Microsoft Corporation
- 当前专利权人: Microsoft Corporation
- 当前专利权人地址: US WA Redmond
- 主分类号: G06F17/30
- IPC分类号: G06F17/30 ; G06F9/46
摘要:
Computational units of any task may run in different silos. In an embodiment, a search query may be evaluated efficiently on a non-uniform memory architecture (NUMA) machine, by assigning separate chunks of the index to separate memories. In a NUMA machine, each socket has an attached memory. The latency time is low or high, depending on whether a processor accesses data in its attached memory or a different memory. Copies of an index manager program, which compares a query to an index, run separately on different processors in a NUMA machine. Each instance of the index manager compares the query to the index chunk in the memory attached to the processor on which that instance is running. Thus, each instance of the index manager may compare a query to a particular portion of the index using low-latency accesses, thereby increasing the efficiency of the search.
公开/授权文献
- US08135723B2 Leveraging low-latency memory access 公开/授权日:2012-03-13