Phase detector circuitry for a phase-locked loop frequency synthesizer, the phase detector circuitry comprising a reference input configured to receive a reference signal; a feedback input configured to receive a divided signal from divider circuitry in a feedback path of the phase-locked loop; and pulse generation circuitry configured to generate control pulses for controlling a charge pump in the phase-locked loop in accordance with a frequency and phase relationship between the reference signal and the divided signal; wherein the divided signal comprises a pulse having a length shorter than a half period of the divided signal, and wherein the pulse generation circuitry is configured to generate the control pulses by masking the reference signal using the pulse of the divided signal as a mask, so as to define the edges of the control pulses from the edges of the divided signal and an edge of the reference signal.