A memory cell array is configured so that a plurality of memory cells which are connected to a word line and a bit line store one value out of n values (n is a natural number of 2 or more) in one memory cell and are arranged in a matrix. A control circuit controls electronic potentials of the word line and the bit line in response to input data to write data in the memory cells. When writing data in the first memory cell of the memory cell array, the control circuit varies a writing level on the basis of writing data to write in a second memory cell adjacent to the first memory cell.