Invention Application
- Patent Title: CLOCK PHASE ALIGNING APPARATUS FOR BURST-MODE DATA
- Patent Title (中): 用于冲击模式数据的时钟相位设备
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Application No.: US12611466Application Date: 2009-11-03
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Publication No.: US20100135666A1Publication Date: 2010-06-03
- Inventor: Jong-deog KIM , Bong-kyu KIM , Quan LE , Kwang-ok KIM , Dong-soo LEE
- Applicant: Jong-deog KIM , Bong-kyu KIM , Quan LE , Kwang-ok KIM , Dong-soo LEE
- Applicant Address: KR Daejeon-si
- Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
- Current Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
- Current Assignee Address: KR Daejeon-si
- Priority: KR10-2008-0119801 20081128; KR10-2009-0026618 20090327
- Main IPC: H04J14/08
- IPC: H04J14/08 ; H04J14/00 ; H04L7/00

Abstract:
Disclosed is a clock phase aligning apparatus capable of synchronizing a clock signal in the middle of an upstream burst mode data bit in an optical line terminal of a passive optical network. The clock phase aligning apparatus effectively aligns a phase of a clock signal with a phase of data during an overhead period of burst mode packet data through an over-sampling scheme and a digital scheme. Burst mode data signals are subject to an over-sampling through a high speed continuous mode analog circuit and then converted into low speed parallel signals through a parallel conversion unit. Such low speed parallel signals are processed with respect to sampling patterns through a digital look-up scheme in a logic circuit device such that the phase of data is arranged with the phase of a clock signal during a limited bit stream specified in a burst mode preamble timing.
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