Invention Application
- Patent Title: POWER-DOWN CIRCUIT WITH SELF-BIASED COMPENSATION CIRCUIT
- Patent Title (中): 具有自偏置补偿电路的掉电电路
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Application No.: US12328305Application Date: 2008-12-04
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Publication No.: US20100141330A1Publication Date: 2010-06-10
- Inventor: Ping-Lin Yang , Hsin-Hsin Ko , Chung-Cheng Chou
- Applicant: Ping-Lin Yang , Hsin-Hsin Ko , Chung-Cheng Chou
- Main IPC: H03K3/01
- IPC: H03K3/01

Abstract:
A circuit includes a first power supply node at a first power supply voltage; a gated-node; and a first control device coupled between the first power supply node and the gated-node. The first control device is configured to pass the first power supply voltage to the gated-node or to disconnect the gated-node from the first power supply voltage. A second control device is coupled between the first power supply node and the gated-node. The second control device is configured to pass a gated-voltage to the gated-node or disconnect the gated-node from the gated-voltage. A voltage-drop device is coupled between the first power supply node and the gated-node, wherein the voltage-drop device is serially connected with the second control device. A negative-feedback current source is connected in parallel with the voltage-drop device. The negative-feedback current source is configured to provide a current tracking a variation of the gated-voltage at the gated-node.
Public/Granted literature
- US07760009B2 Power-down circuit with self-biased compensation circuit Public/Granted day:2010-07-20
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