An architecture for processing signal communications between a frequency translation module and an integrated receiver decoder. According to an exemplary embodiment, the signal processing apparatus comprises a demodulator for generating a first signal responsive to an FSK signal, said first signal comprising a varying amplitude and a clamping means for generating a second signal, wherein said second signal has a first value when the amplitude of the first signal is above a predetermined value, and wherein said second signal has a second value when the amplitude is below a second predetermined value.