Invention Application
- Patent Title: Method for Improving Power-Supply Rejection
- Patent Title (中): 改善电源抑制的方法
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Application No.: US12353843Application Date: 2009-01-14
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Publication No.: US20100176875A1Publication Date: 2010-07-15
- Inventor: Srinivas K. Pulijala , Paul F. Illegems
- Applicant: Srinivas K. Pulijala , Paul F. Illegems
- Main IPC: G05F1/10
- IPC: G05F1/10

Abstract:
An electronic circuit may comprise an input stage powered by a supply voltage and configured to receive a reference signal. The circuit may further comprise an output stage powered by the supply voltage and coupled to the input stage, and configured to generate an error signal based on: the reference signal, and a feedback signal based on an output signal. The circuit may also include a pass transistor powered by the supply voltage and configured to generate the output signal based on the error signal. A capacitor coupled between the supply voltage and the output stage may increase the current flowing in the output stage, resulting in the output stage conducting current even during a rising edge of the supply voltage, preventing the output signal from reaching the level of the supply voltage during the rising edge of the supply voltage.
Public/Granted literature
- US07907003B2 Method for improving power-supply rejection Public/Granted day:2011-03-15
Information query
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