发明申请
- 专利标题: BIT SET MODES FOR A RESISTIVE SENSE MEMORY CELL ARRAY
- 专利标题(中): 用于电阻式感应存储器单元阵列的位设置模式
-
申请号: US12352693申请日: 2009-01-13
-
公开(公告)号: US20100177551A1公开(公告)日: 2010-07-15
- 发明人: Yiran Chen , Daniel S. Reed , Yong Lu , Harry Hongyue Liu , Hai Li , Rod V. Bowman
- 申请人: Yiran Chen , Daniel S. Reed , Yong Lu , Harry Hongyue Liu , Hai Li , Rod V. Bowman
- 申请人地址: US CA Scotts Valley
- 专利权人: Seagate Technology LLC
- 当前专利权人: Seagate Technology LLC
- 当前专利权人地址: US CA Scotts Valley
- 主分类号: G11C11/00
- IPC分类号: G11C11/00 ; G11C11/416
摘要:
Various embodiments of the present invention are generally directed to a method and apparatus for providing different bit set modes for a resistive sense memory (RSM) array, such as a spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM) array. In accordance with some embodiments, a group of RSM cells in a non-volatile semiconductor memory array is identified for application of a bit set operation. A bit set value is selected from a plurality of bit set values each separately writable to the RSM cells to place said cells in a selected resistive state. The selected bit set value is thereafter written to at least a portion of the RSM cells in the identified group.
公开/授权文献
- US08040713B2 Bit set modes for a resistive sense memory cell array 公开/授权日:2011-10-18
信息查询