Invention Application
- Patent Title: METHOD OF MANUFACTURING CMOS TRANSISTOR
- Patent Title (中): 制造CMOS晶体管的方法
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Application No.: US12479112Application Date: 2009-06-05
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Publication No.: US20100178754A1Publication Date: 2010-07-15
- Inventor: Jun-youl Yang , Byoung-moon Yoon , Cheol-woo Park , Won-jun Lee , Ki-hyung Ko
- Applicant: Jun-youl Yang , Byoung-moon Yoon , Cheol-woo Park , Won-jun Lee , Ki-hyung Ko
- Applicant Address: KR Gyeonggi-do
- Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee Address: KR Gyeonggi-do
- Priority: KR10-2009-0001940 20090109
- Main IPC: H01L21/8238
- IPC: H01L21/8238 ; H01L21/20

Abstract:
A method of manufacturing a complementary metal-oxide semiconductor (CMOS) transistor includes: forming a semiconductor layer in which an n-MOS transistor region and a p-MOS transistor region are defined; forming an insulation layer on the semiconductor layer; forming a conductive layer on the insulation layer; forming a mask pattern exposing the n-MOS transistor region, on the conductive layer; generating a damage region in an upper portion of the conductive layer by implanting impurities in the conductive layer of the n-MOS transistor region using the mask pattern as a mask; removing the mask pattern; removing the damage region; and patterning the conductive layer to form an n-MOS transistor gate and a p-MOS transistor gate. Accordingly, gate thinning and formation of a step between the n-MOS transistor region gate and the p-MOS transistor region gate can be prevented.
Information query
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