发明申请
US20100190352A1 USE OF A BIASED PRECOAT FOR REDUCED FIRST WAFER DEFECTS IN HIGH-DENSITY PLASMA PROCESS
有权
在高密度等离子体过程中减少第一波形缺陷的偏置预处理的使用
- 专利标题: USE OF A BIASED PRECOAT FOR REDUCED FIRST WAFER DEFECTS IN HIGH-DENSITY PLASMA PROCESS
- 专利标题(中): 在高密度等离子体过程中减少第一波形缺陷的偏置预处理的使用
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申请号: US12362320申请日: 2009-01-29
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公开(公告)号: US20100190352A1公开(公告)日: 2010-07-29
- 发明人: Rajneesh JAISWAL
- 申请人: Rajneesh JAISWAL
- 主分类号: H01L21/31
- IPC分类号: H01L21/31 ; B05D3/06
摘要:
According to various embodiments, the present teachings include methods for reducing first wafer defects in a high-density plasma chemical vapor deposition process. In an exemplary embodiment, the method can include running a deposition chamber for deposition of film on a first batch of silicon wafers and then cleaning interior surfaces of the deposition chamber. The method can further include inserting a protective electrostatic chuck cover (PEC) wafer on an electrostatic chuck in the deposition chamber and applying power to bias the PEC wafer while simultaneously precoating the deposition chamber with an oxide. The exemplary method can also include re-starting the deposition chamber for deposition of film on a second batch of silicon wafers.
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