发明申请
US20100195776A1 Systems and Methods for Synchronous, Retimed Analog to Digital Conversion 失效
用于同步,重定时模数转换的系统和方法

  • 专利标题: Systems and Methods for Synchronous, Retimed Analog to Digital Conversion
  • 专利标题(中): 用于同步,重定时模数转换的系统和方法
  • 申请号: US12669482
    申请日: 2008-06-06
  • 公开(公告)号: US20100195776A1
    公开(公告)日: 2010-08-05
  • 发明人: Erik ChmelarChoshu ItoWilliam Loh
  • 申请人: Erik ChmelarChoshu ItoWilliam Loh
  • 国际申请: PCT/US08/66074 WO 20080606
  • 主分类号: H04L7/02
  • IPC分类号: H04L7/02 H03K5/153
Systems and Methods for Synchronous, Retimed Analog to Digital Conversion
摘要:
Various embodiments of the present invention provide systems and methods for analog to digital conversion. For example, a latch based analog to digital converter is disclosed that includes a first interleave with a set of comparators, a selector circuit and a latch. The set of comparators is operable to compare an analog input with respective reference voltages, and is synchronized to a clock phase. The selector circuit is operable to select an output of one of the set of comparators based at least in part on a selector input. A first interleave output is derived from the selected output. The latch receives a second interleave output from a second interleave and is transparent when the clock phase is asserted. The selector input includes an output of the latch.
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