发明申请
US20100200951A1 Method of Forming Top Electrode for Capacitor and Interconnection in Integrated Passive Device (IPD) 有权
在集成无源器件(IPD)中形成电容器和互连顶电极的方法

  • 专利标题: Method of Forming Top Electrode for Capacitor and Interconnection in Integrated Passive Device (IPD)
  • 专利标题(中): 在集成无源器件(IPD)中形成电容器和互连顶电极的方法
  • 申请号: US12763386
    申请日: 2010-04-20
  • 公开(公告)号: US20100200951A1
    公开(公告)日: 2010-08-12
  • 发明人: Yaojian LinRobert Charles Frye
  • 申请人: Yaojian LinRobert Charles Frye
  • 申请人地址: SG Singapore
  • 专利权人: STATS CHIPPAC, LTD.
  • 当前专利权人: STATS CHIPPAC, LTD.
  • 当前专利权人地址: SG Singapore
  • 主分类号: H01L23/522
  • IPC分类号: H01L23/522
Method of Forming Top Electrode for Capacitor and Interconnection in Integrated Passive Device (IPD)
摘要:
A method of manufacturing a semiconductor device includes providing a substrate having a first conductive layer disposed on a top surface of the substrate. A high resistivity layer is formed over the substrate and the first conductive layer. A dielectric layer is deposited over the substrate, first conductive layer and high resistivity layer. A portion of the dielectric layer, high resistivity layer, and first conductive layer forms a capacitor stack. A first passivation layer is formed over the dielectric layer. A second conductive layer is formed over the capacitor stack and a portion of the first passivation layer. A first opening is etched in the dielectric layer to expose a surface of the high resistivity layer. A third and fourth conductive layer is deposited over the first opening in the dielectric layer and a portion of the first passivation layer.
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