发明申请
- 专利标题: SYSTEM AND METHOD FOR DEMONSTRATING THE CORRECTNESS OF AN EXECUTION TRACE IN CONCURRENT PROCESSING ENVIRONMENTS
- 专利标题(中): 用于演示相关处理环境中执行跟踪的正确性的系统和方法
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申请号: US12370048申请日: 2009-02-12
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公开(公告)号: US20100205484A1公开(公告)日: 2010-08-12
- 发明人: Kristijan Dragicevic , Luis Garces-Erice , Daniel Nikolaus Bauer
- 申请人: Kristijan Dragicevic , Luis Garces-Erice , Daniel Nikolaus Bauer
- 申请人地址: US NY Armonk
- 专利权人: INTERNATIONAL BUSINESS MACHINES CORPORATION
- 当前专利权人: INTERNATIONAL BUSINESS MACHINES CORPORATION
- 当前专利权人地址: US NY Armonk
- 主分类号: G06F11/28
- IPC分类号: G06F11/28
摘要:
Since multi-core processors have become the standard architecture for general purpose machines, programmers are required to write software optimized for parallelism. Verification of correctness is an important issue for parallel code because of its complexity. There are still tools missing that provide verification for complex code, such as testing the execution of code provides. Consequently, described herein are systems and methods to evaluate the correctness of program traces. Furthermore, the systems and methods described herein do not demand excessive computational requirements and the size of the program trace being evaluated increases.
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