发明申请
US20100207162A1 VERTICAL AND TRENCH TYPE INSULATED GATE MOS SEMICONDUCTOR DEVICE
有权
垂直和倾斜型绝缘栅MOS半导体器件
- 专利标题： VERTICAL AND TRENCH TYPE INSULATED GATE MOS SEMICONDUCTOR DEVICE
- 专利标题（中）： 垂直和倾斜型绝缘栅MOS半导体器件
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申请号： US12767356申请日： 2010-04-26
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公开(公告)号： US20100207162A1公开(公告)日： 2010-08-19
- 发明人: Koh YOSHIKAWA , Hiroki WAKIMOTO , Masahito OTSUKI
- 申请人： Koh YOSHIKAWA , Hiroki WAKIMOTO , Masahito OTSUKI
- 申请人地址： JP Shinagawa-ku
- 专利权人： FUJI ELECTRIC SYSTEMS CO., LTD.
- 当前专利权人： FUJI ELECTRIC SYSTEMS CO., LTD.
- 当前专利权人地址： JP Shinagawa-ku
- 优先权： JP2006-122811 20060427; JP2006-187439 20060707; JP2007-058029 20070308
- 主分类号： H01L29/739
- IPC分类号： H01L29/739
摘要：
A vertical and trench type insulated gate MOS semiconductor device is provided in which the surfaces of p-type channel regions and the surfaces of portions of an n-type semiconductor substrate alternate in the longitudinal direction of the trench between the trenches arranged in parallel, and an n+-type emitter region selectively formed on the surface of the p-type channel region is wide by the side of the trench and becomes narrow toward the center point between the trenches. This enables the device to achieve low on-resistance and enhanced turn-off capability.
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