Invention Application
- Patent Title: Junction Profile Engineering Using Staged Thermal Annealing
- Patent Title (中): 接头型材工程使用分段热退火
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Application No.: US12618052Application Date: 2009-11-13
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Publication No.: US20100210086A1Publication Date: 2010-08-19
- Inventor: Li-Ting Wang , Keh-Chiang Ku , Yu-Chang Lin , Nai-Han Cheng , Li-Ping Huang
- Applicant: Li-Ting Wang , Keh-Chiang Ku , Yu-Chang Lin , Nai-Han Cheng , Li-Ping Huang
- Main IPC: H01L21/336
- IPC: H01L21/336

Abstract:
An annealing method includes performing an activation annealing on a wafer with a peak temperature of greater than about 1200° C., wherein the activation annealing has a first duration; and performing a defect-recovery annealing on the wafer at a defect-recovery temperature lower than the peak temperature for a second duration. The second duration is longer than the first duration. The annealing method includes no additional annealing steps at temperatures greater than about 1200° C., and no room-temperature cooling step exists between the activation annealing and the defect-recovery annealing.
Public/Granted literature
- US08058134B2 Junction profile engineering using staged thermal annealing Public/Granted day:2011-11-15
Information query
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