Invention Application
US20100210086A1 Junction Profile Engineering Using Staged Thermal Annealing 有权
接头型材工程使用分段热退火

Junction Profile Engineering Using Staged Thermal Annealing
Abstract:
An annealing method includes performing an activation annealing on a wafer with a peak temperature of greater than about 1200° C., wherein the activation annealing has a first duration; and performing a defect-recovery annealing on the wafer at a defect-recovery temperature lower than the peak temperature for a second duration. The second duration is longer than the first duration. The annealing method includes no additional annealing steps at temperatures greater than about 1200° C., and no room-temperature cooling step exists between the activation annealing and the defect-recovery annealing.
Public/Granted literature
Information query
Patent Agency Ranking
0/0