发明申请
US20100214864A1 MEMORY DEVICE COMMAND DECODING SYSTEM AND MEMORY DEVICE AND PROCESSOR-BASED SYSTEM USING SAME
有权
存储器件命令解码系统和存储器件以及使用该处理器的系统
- 专利标题: MEMORY DEVICE COMMAND DECODING SYSTEM AND MEMORY DEVICE AND PROCESSOR-BASED SYSTEM USING SAME
- 专利标题(中): 存储器件命令解码系统和存储器件以及使用该处理器的系统
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申请号: US12776154申请日: 2010-05-07
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公开(公告)号: US20100214864A1公开(公告)日: 2010-08-26
- 发明人: Scott Smith , Duc Ho , J. Thomas Pawlowski
- 申请人: Scott Smith , Duc Ho , J. Thomas Pawlowski
- 申请人地址: US ID Boise
- 专利权人: Micron Technology, Inc.
- 当前专利权人: Micron Technology, Inc.
- 当前专利权人地址: US ID Boise
- 主分类号: G11C8/10
- IPC分类号: G11C8/10 ; G11C7/00 ; G11C5/14
摘要:
Systems, devices and methods are disclosed. In an embodiment of one such device, an embodiment of a memory device includes a command decoder that is operable to decode received write enable, row address strobe and column address strobe signals to place the memory device in at least one reduced power state despite the absence of either a clock enable signal or a chip select signal. The command decoder performs this function by decoding the write enable, row address strobe and column address strobe signals in combination with at least one address signal received by the memory device. The command decoder can also decode a no operation command, which differs from the at least one reduced power state by only the state of the write enable signal. As a result, when the at least one reduced power state is terminated by a transition of the write enable signal, the memory device automatically transitions to a no operation mode.