发明申请
US20100238598A1 Electrostatic Discharge Power Clamp Trigger Circuit Using Low Stress Voltage Devices
有权
使用低应力电压器件的静电放电电源钳位触发电路
- 专利标题: Electrostatic Discharge Power Clamp Trigger Circuit Using Low Stress Voltage Devices
- 专利标题(中): 使用低应力电压器件的静电放电电源钳位触发电路
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申请号: US12406684申请日: 2009-03-18
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公开(公告)号: US20100238598A1公开(公告)日: 2010-09-23
- 发明人: Yikai Liang , Arvind Bomdica , Samudyatha Suryanarayana , Gayatri Gopalan , Min Xu , Xin Liu , Ming-Ju Edward Lee
- 申请人: Yikai Liang , Arvind Bomdica , Samudyatha Suryanarayana , Gayatri Gopalan , Min Xu , Xin Liu , Ming-Ju Edward Lee
- 申请人地址: US CA Sunnyvale
- 专利权人: ADVANCED MICRO DEVICES, INC.
- 当前专利权人: ADVANCED MICRO DEVICES, INC.
- 当前专利权人地址: US CA Sunnyvale
- 主分类号: H02H9/04
- IPC分类号: H02H9/04 ; G06F17/00
摘要:
Embodiments of an IC protection circuit that protects low voltage supply transistors and circuits within the IC from excessive power supply levels and ESD events are described. A protection circuit situated between the IO pins of the IC and the internal circuitry of the IC includes a voltage drop network and a plurality of shunt circuits to protect the IC against excessive supply voltages and ESD voltages. Each shunt circuit includes an RC trigger stage and an NMOS shunt stage that are made using low-voltage devices. A protection circuit of the embodiments includes a high voltage IO pin interface, a voltage drop network coupled to the IO pin and comprising a plurality of forward-biased diodes connected in series to drop a high voltage on the IO pin to a low voltage level, an NMOS shunt transistor coupled between the voltage drop network and a ground terminal, and a trigger circuit coupled to the NMOS shunt transistor to activate the shunt transistor when a sensed input voltage rise time is shorter than a defined supply voltage rise time.
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