发明申请
US20100246279A1 Pipe latch circuit and semiconductor memory device using the same 有权
管路锁存电路和使用其的半导体存储器件

Pipe latch circuit and semiconductor memory device using the same
摘要:
A pipe latch circuit comprises a reset signal generating unit which receives a read-write flag signal and a read period signal and generates a reset signal, wherein the reset signal is enabled upon entry into a write operation or after all data are outputted to an outside upon read operation, an input/output control signal generating unit which generates a plurality of input control signals and output control signals in response to a read strobe signal and a clock signal, and is reset in response to the reset signal, and a pipe latch unit which latches inputted data in response to the input control signals and outputs the latched data in response to the output control signals.
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