发明申请
US20100250223A1 SEMICONDUCTOR CIRCUIT DETERIORATION SIMULATION METHOD AND COMPUTER PROGRAM MEDIUM
审中-公开
半导体电路测量模拟方法和计算机程序介质
- 专利标题： SEMICONDUCTOR CIRCUIT DETERIORATION SIMULATION METHOD AND COMPUTER PROGRAM MEDIUM
- 专利标题（中）： 半导体电路测量模拟方法和计算机程序介质
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申请号： US12652434申请日： 2010-01-05
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公开(公告)号： US20100250223A1公开(公告)日： 2010-09-30
- 发明人: Daisuke Hagishima , Kazuya Matsuzawa , Yuichiro Mitani , Shigeto Fukatsu , Kouichirou Inoue
- 申请人： Daisuke Hagishima , Kazuya Matsuzawa , Yuichiro Mitani , Shigeto Fukatsu , Kouichirou Inoue
- 专利权人： Kabushiki Kaisha Toshiba
- 当前专利权人： Kabushiki Kaisha Toshiba
- 优先权： JP2009-073907 20090325
- 主分类号： G06F17/50
- IPC分类号： G06F17/50
摘要：
A semiconductor circuit deterioration simulation method for a circuit including MOSFETs includes inserting a dynamic voltage source associated with a fluctuation in voltage/current characteristics into each gate terminal of a plurality of MOSFETs in series, calculating dynamic deterioration amounts of the plurality of MOSFETs by performing circuit simulation and calculating a dynamic deterioration amount, and repeating the above processing to perform the circuit deterioration simulation over the long term.
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