发明申请
US20100251016A1 Issuing Instructions In-Order in an Out-of-Order Processor Using False Dependencies 有权
在使用虚假依赖关系的乱序处理器中发布使用说明书

Issuing Instructions In-Order in an Out-of-Order Processor Using False Dependencies
摘要:
A mechanism is provided for issuing instructions. An instruction dispatch unit receives an instruction for dispatch to one of a plurality of execution units. The instruction dispatch unit analyzes a tag register to determine whether a previous tag associated with a previous instruction has been stored in the tag register. Responsive to the previous tag associated with the previous instruction failing to be stored in the tag register, the instruction dispatch unit storing a tag corresponding to the instruction in the tag register. The instruction dispatch unit dispatches the instruction to an issue queue for issue to the one of the plurality of execution units.
信息查询
0/0