Invention Application
US20100289130A1 Method and Apparatus for Vertical Stacking of Integrated Circuit Chips
审中-公开
集成电路芯片垂直堆叠的方法和装置
- Patent Title: Method and Apparatus for Vertical Stacking of Integrated Circuit Chips
- Patent Title (中): 集成电路芯片垂直堆叠的方法和装置
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Application No.: US12464253Application Date: 2009-05-12
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Publication No.: US20100289130A1Publication Date: 2010-11-18
- Inventor: Joseph C. Fjelstad
- Applicant: Joseph C. Fjelstad
- Applicant Address: US CA Cupertino
- Assignee: INTERCONNECT PORTFOLIO LLC
- Current Assignee: INTERCONNECT PORTFOLIO LLC
- Current Assignee Address: US CA Cupertino
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H05K1/11 ; H01L21/50

Abstract:
A method and apparatus for constructing a packaged integrated circuit stack 40 having at least two packaged integrated circuits 44 and 45 with an interposer 42 between the packaged integrated circuits 44 and 45. Interposer 42 is provided with apertures 47 which allow adhesive 50 to flow through interposer 42 to bond packaged integrated circuits 44 and 45 together with interposer 42. Alternate embodiments provide holes 54 to allow passage of leads 56 through interposer 42 to a substrate 60 through additional connections 48. The method describes the construction of the stack.
Information query
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