发明申请
US20100314711A1 3D INTEGRATED CIRCUIT DEVICE HAVING LOWER-COST ACTIVE CIRCUITRY LAYERS STACKED BEFORE HIGHER-COST ACTIVE CIRCUITRY LAYER
有权
具有低成本有源电路层的3D集成电路器件在高成本有源电路层之前堆叠
- 专利标题： 3D INTEGRATED CIRCUIT DEVICE HAVING LOWER-COST ACTIVE CIRCUITRY LAYERS STACKED BEFORE HIGHER-COST ACTIVE CIRCUITRY LAYER
- 专利标题（中）： 具有低成本有源电路层的3D集成电路器件在高成本有源电路层之前堆叠
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申请号： US12194211申请日： 2008-08-19
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公开(公告)号： US20100314711A1公开(公告)日： 2010-12-16
- 发明人: Mukta G. Farooq , Robert Hannon , Subramanian S. Iyer , Steven J. Koester , Fei Liu , Sampath Purushothaman , Albert M. Young , Roy R. Yu
- 申请人： Mukta G. Farooq , Robert Hannon , Subramanian S. Iyer , Steven J. Koester , Fei Liu , Sampath Purushothaman , Albert M. Young , Roy R. Yu
- 申请人地址： US NY Armonk
- 专利权人： International Business Machines Corporation
- 当前专利权人： International Business Machines Corporation
- 当前专利权人地址： US NY Armonk
- 主分类号： H01L27/12
- IPC分类号： H01L27/12 ; H01L21/768
摘要：
A method is provided for fabricating a 3D integrated circuit structure. According to the method, a first active circuitry layer wafer that includes active circuitry is provided, and a first portion of the first active circuitry layer wafer is removed such that a second portion of the first active circuitry layer wafer remains. Another wafer that includes active circuitry is provided, and the other wafer is bonded to the second portion of the first active circuitry layer wafer. The first active circuitry layer wafer is lower-cost than the other wafer. Also provided are a tangible computer readable medium encoded with a program for fabricating a 3D integrated circuit structure, and a 3D integrated circuit structure.
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