发明申请
US20100327377A1 Fermi-level unpinning structures for semiconductive devices, processes of forming same, and systems containing same
有权
用于半导体器件的费米级裸露结构，其形成方法以及含有它们的体系
- 专利标题： Fermi-level unpinning structures for semiconductive devices, processes of forming same, and systems containing same
- 专利标题（中）： 用于半导体器件的费米级裸露结构，其形成方法以及含有它们的体系
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申请号： US12459254申请日： 2009-06-26
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公开(公告)号： US20100327377A1公开(公告)日： 2010-12-30
- 发明人: Gilbert Dewey , Niloy Mukherjee , Matthew Metz , Jack T. Kavalieros , Nancy M. Zelick , Robert S. Chau
- 申请人： Gilbert Dewey , Niloy Mukherjee , Matthew Metz , Jack T. Kavalieros , Nancy M. Zelick , Robert S. Chau
- 主分类号： H01L29/78
- IPC分类号： H01L29/78 ; H01L29/06 ; H01L21/31 ; H01L21/3205
摘要：
An interlayer is used to reduce Fermi-level pinning phenomena in a semiconductive device with a semiconductive substrate. The interlayer may be a rare-earth oxide. The interlayer may be an ionic semiconductor. A metallic barrier film may be disposed between the interlayer and a metallic coupling. The interlayer may be a thermal-process combination of the metallic barrier film and the semiconductive substrate. A process of forming the interlayer may include grading the interlayer. A computing system includes the interlayer.
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