发明申请
US20110001184A1 METHOD OF ADJUSTING THE THRESHOLD VOLTAGE OF A TRANSISTOR BY A BURIED TRAPPING LAYER
有权
通过一个BURIED TRAPPING层调整晶体管的阈值电压的方法
- 专利标题： METHOD OF ADJUSTING THE THRESHOLD VOLTAGE OF A TRANSISTOR BY A BURIED TRAPPING LAYER
- 专利标题（中）： 通过一个BURIED TRAPPING层调整晶体管的阈值电压的方法
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申请号： US12865549申请日： 2009-02-11
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公开(公告)号： US20110001184A1公开(公告)日： 2011-01-06
- 发明人: Francois Andrieu , Emmanuel Augendre , Laurent Clavelier , Marek Kostrzewa
- 申请人： Francois Andrieu , Emmanuel Augendre , Laurent Clavelier , Marek Kostrzewa
- 优先权： FR0851073 20080219
- 国际申请： PCT/FR09/50212 WO 20090211
- 主分类号： H01L29/792
- IPC分类号： H01L29/792 ; H01L21/336
摘要：
An electronic subassembly and associated method for the production of an electronic subassembly include a semiconductor layer bearing at least a first transistor having an adjustable threshold voltage is joined to an insulator layer and a in which a first trapping zone is formed at a predetermined first depth. The first trapping zone extends at least beneath a channel of the first transistor and includes traps of greater density than the density of traps outside the first trapping zone, in such a way that the semiconductor layer and the first trapping zone are capacitively coupled. The useful information from the first transistor includes the charge transport within this transistor. A second trapping zone can be formed that extends at least beneath a channel of a second transistor that is formed by a second implantation with an energy and/or a dose and/or atoms that differ from those used to form the first trapping zone.
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