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发明申请
US20110007549A1 SHARED BIT LINE AND SOURCE LINE RESISTIVE SENSE MEMORY STRUCTURE 有权
共享位线和源线电阻感知存储器结构

SHARED BIT LINE AND SOURCE LINE RESISTIVE SENSE MEMORY STRUCTURE
摘要：
A resistive sense memory apparatus includes a first semiconductor transistor having a first contact electrically connected to a first source line and a second contact electrically connected to a first resistive sense memory element and a second semiconductor transistor having a first contact electrically connected to a second source line and a second contact electrically connected to a second resistive sense memory element. A bit line is electrically connected to the first resistive sense memory element and the second resistive sense memory element.
摘要（中）：

电阻式感测存储装置包括第一半导体晶体管，其具有电连接到第一源极线的第一接触点和电连接到第一电阻性感测存储元件的第二接触点，以及第二半导体晶体管，其具有电连接到第二源极线 以及电连接到第二电阻读出存储元件的第二触点。 位线电连接到第一电阻读出存储器元件和第二电阻读出存储元件。

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