A circuit for a high-density data recording channel includes a first data detector, a second data detector, one or more multiplexers and a sequence identifier. The first data detector generates a first data detector output, and the second data detector generates a second data detector output. The multiplexers change between a first mode and a second mode to alternately receive the first data detector output and the second data detector output. The sequence identifier receives a data sequence including at least one of a first data sequence, such as VFO data, and a second data sequence, such as random data. The second data sequence includes a greater number of signal levels than the first data sequence. The sequence identifier changes the multiplexers between the first mode and the second mode based on whether the data sequence is the first data sequence or the second data sequence. The data sequence includes a plurality of timing stages. The sequence detector can at least partially control a loop bandwidth of the circuit based on the timing stage of the data sequence.